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W40S11-02
SDRAM Buffer - 2 DIMM (Mobile)
Features
* Ten skew-controlled CMOS outputs (SDRAM0:9) * Supports two SDRAM DIMMs * Ideal for high-performance systems designed around Intel(R)'s latest mobile chip set * SMBus serial configuration interface * Skew between any two outputs is less than 250 ps * 1 to 5 ns propagation delay * DC to 133-MHz operation * Single 3.3V supply voltage * Low power CMOS design packaged in a 28-pin, 209-mil SSOP (Shrink Small Outline Package)
Key Specifications
Supply Voltages: ........................................... VDD = 3.3V5% Operating Temperature:.................................... 0C to +70C Input Threshold:...................................................1.5V typical Maximum Input Voltage: ...................................... VDD + 0.5V Input Frequency:...............................................0 to 133 MHz BUF_IN to SDRAM0:9 Propagation Delay:........ 1.0 to 5.0 ns Output Edge Rate: ................................................. >1.5 V/ns Output Skew: ............................................................ 250 ps Output Duty Cycle:...................................45/55% worst case Output Impedance: ....................................... 15 ohms typical Output Type: ............................................... CMOS rail-to-rail
Overview
The Cypress W40S11-02 is a low-voltage, ten-output clock buffer. Output buffer impedance is approximately 15 , which is ideal for driving SDRAM DIMMs.
Block Diagram
Pin Configuration
SDATA SCLOCK
Serial Port
Device Control OE SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8
VDD SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 GND BUF_IN VDD SDRAM8 GND VDD SDATA [1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD SDRAM7 SDRAM6 GND VDD SDRAM5 SDRAM4 GND OE [1] VDD SDRAM9 GND GND SCLOCK[1]
BUF_IN
SDRAM9
Note: 1. Internal pull-up resistor of 250K on SDATA, SCLOCK, and OE inputs (should not be relied upon for pulling up to VDD).
Rev 1.0, Dec. 01, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 9
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W40S11-02
Pin Definitions
Pin Name SDRAM0:9 Pin No. 2, 3, 6, 7, 22, 23, 26, 27, 11, 18 9 14 15 1, 5, 10, 13, 19, 24, 28 4, 8, 12, 16, 17, 21, 25 20 Pin Type O Pin Description SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to within 250 ps of each other. Clock Input: This clock input has an input threshold voltage of 1.5V (typ). SMBus Data Input: Data should be presented to this input as described in the SMBus section of this data sheet. Internal 250-k pull-up resistor. SMBus Clock Input: The SMBus Data clock should be presented to this input as described in the SMBus section of this data sheet. Internal 250-k pull-up resistor. Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane. Output Enable: Internal 250-k pull-up resistor. Three-states outputs when LOW.
BUF_IN SDATA SCLOCK VDD GND OE
I I/O I P G I
Functional Description
Output Control Pins Outputs three-stated when OE = 0, and toggle when OE = 1. Outputs are in phase with BUF_IN but are phase delayed by 1 to 5 ns. Outputs can also be controlled via the SMBus interface.
Output Drivers The W40S11-02 output buffers are CMOS type which deliver a rail-to-rail (GND to VDD) output voltage swing into a nominal capacitive load. Thus, output signaling is both TTL and CMOS level compatible. Nominal output buffer impedance is 15 ohms. Operation Data is written to the W40S11-02 in ten bytes of eight bits each. Bytes are written in the order shown in Table 1.
Table 1. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W40S11-02 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W40S11-02 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W40S11-02, therefore bit values are ignored ("Don't Care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W40S11-02, therefore bit values are ignored ("Don't Care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal W40S11-23 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 2, Data Byte Serial Configuration Map. Refer to Cypress clock drivers.
2
Command Code
"Don't Care"
3
Byte Count
"Don't Care"
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 2
Don't Care
Rev 1.0, Dec. 01, 2006
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W40S11-02
Writing Data Bytes Each bit in the data bytes control a particular device function. Bits are written most significant bit (MSB) first, which is bit 7. Table 2. Data Bytes 0-2 Serial Configuration Map[2] Affected Pin Bit(s) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Pin No. N/A N/A N/A N/A 7 6 3 2 27 26 23 22 N/A N/A N/A N/A 18 11 N/A N/A N/A N/A N/A N/A Pin Name Reserved Reserved Reserved Reserved SDRAM3 SDRAM2 SDRAM1 SDRAM0 SDRAM7 SDRAM6 SDRAM5 SDRAM4 Reserved Reserved Reserved Reserved SDRAM9 SDRAM8 Reserved Reserved Reserved Reserved Reserved Reserved Control Function (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 0 ----Low Low Low Low Low Low Low Low ----Low Low ------Data Byte 0 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable) ----Active Active Active Active Active Active Active Active ----Active Active ------Bit Control 1 Table 2 gives the bit formats for registers located in Data Bytes 0-6.
Data Byte 1 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
Data Byte 2 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
Note: 2. At power-up all SDRAM outputs are enabled and active. It is recommended to program Bits 4-7 of Byte0 and Bits 0-3 of Byte1 to a "0" to save power and reduce noise.
Rev 1.0, Dec. 01, 2006
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W40S11-02
How To Use the Serial Data Interface
Electrical Requirements Figure 1 illustrates electrical characteristics for the serial interface bus used with the W40S11-02. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resistor on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data. Although the W40S11-02 is a receive-only device (no data write-back capability), it does transmit an "acknowledge" data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance.
VDD
VDD
~ 2k SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE
~ 2k
SDCLK CLOCK IN CLOCK OUT N DATA IN DATA OUT
SDATA CLOCK IN N
SCLOCK DATA IN DATA OUT
SDATA
N
CHIP SET (SERIAL BUS MASTER TRANSMITTER)
CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER)
Figure 1. Serial Interface Bus Electrical Characteristics
Rev 1.0, Dec. 01, 2006
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W40S11-02
Signaling Requirements As shown in Figure 2, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) pulse. A transitioning data line during a clock HIGH pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). A write sequence is initiated by a "start bit" as shown in Figure 1. A "stop bit" signifies that a transmission has ended. As stated previously, the W40S11-02 sends an "acknowledge" pulse after receiving eight data bits in each byte as shown in Figure 2. Sending Data to the W40S11-02 The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition).
SDATA
SCLOCK
Valid Data Bit
Change of Data Allowed
Figure 2. Serial Data Bus Valid Data Bit
SDATA
SCLOCK Start Bit Stop Bit
Figure 1. Serial Data Bus Start and Stop Bit
Rev 1.0, Dec. 01, 2006
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W40S11-02
Signaling from System Core Logic Start Condition Slave Address (First Byte)
SDATA MSB 1 1 0 1 0 0 1 LSB 0 MSB
Stop C Command Code (Second Byte)
LSB
Byte Count (Third Byte)
MSB MSB
Last Data Byte (Last Byte)
LS
SCLOCK
1
2
3
4
5
6
7
8
A
1
2
3
4
5
6
7
8
A
1
2
3
4
1
2
3
4
5
6
7
8
SDATA
Signaling by Clock Device
Acknowledgment Bit from Clock Device
Figure 2. Serial Data Bus Write Sequence
SDATA tSPF tLOW SCLOCK tSTHD tR tHIGH tF tDSU tDHD tSP tSPSU tSTHD tSPSU
Figure 3. Serial Data Bus Timing Diagram
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condiParameter VDD, VIN TSTG TA TB Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 Unit V C C C
Rev 1.0, Dec. 01, 2006
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W40S11-02
DC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V5%
Parameter IDD IDD IDD Tristate Logic Inputs VIL VIH IILEAK IILEAK VOL VOH IOL IOH CIN COUT LIN Input Low Voltage Input High Voltage Input Leakage Current, BUF_IN Input Leakage Current[3]
[4]
Description 3.3V Supply Current 3.3V Supply Current 3.3V Supply Current in Three-State
Test Condition/Comments at 66 MHz at 100 MHz
Min
Typ 120 185 5
Max 160 220 10
Unit mA mA mA
VSS - 0.3 2.0 -5 -20 IOL = 1 mA IOH = -1 mA VOL = 1.5V VOH = 1.5V 3.1 70 65 110 100
0.8 VDD + 0.5 +5 +5 50 185 160 5 6 7
V V A A mV V mA mA pF pF nH
Logic Outputs (SDRAM0:9)
Output Low Voltage Output High Voltage Output Low Current Output High Current Input Pin Capacitance Output Pin Capacitance Input Pin Inductance
Pin Capacitance/Inductance
Note: 3. OE, SDATA, and SCLOCK logic pins have a 250-k internal pull-up resistor (VDD - 0.8V). 4. All SDRAM outputs loaded by 6" transmission lines with 22-pF capacitors on ends.
AC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V5% (Lump Capacitance Test Load = 30 pF)
Parameter fIN tR tF tSR tSF tEN tDIS tPR tPF tD Zo Description Input Frequency Output Rise Edge Rate Output Fall Edge Rate Output Skew, Rising Edges Output Skew, Falling Edges Output Enable Time Output Disable Time Rising Edge Propagation Delay Falling Edge Propagation Delay Duty Cycle AC Output Impedance Measured at 1.5V 1.0 1.0 1.0 1.0 45 15 Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Test Condition Min 0 1.5 1.5 Typ Max 133 4.0 4.0 250 250 8.0 8.0 5.0 5.0 55 Unit MHz V/ns V/ns ps ps ns ns ns ns %
Rev 1.0, Dec. 01, 2006
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W40S11-02
Layout Example
+3.3V Supply FB
VDDQ3
.005 F 10 F
C4 G G
C3
G
G
G
G
1 2 3 4 5 6 7 8 9 10 11 12 13 14
V
V
V
V
V
V
V
28 27 26 25 24 23 22 21 20 19 18 17 16 15
G
W40S11-02
G
G
FB = Dale ILB1206 - 300 (300 Ceramic Caps C3 = 10-22 F G = VIA to GND plane layer
@ 100 MHz) C4 = 0.005 F V = VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors All VDDs have -1 mF low ESR bypass at pin to ground All bypass caps = 0.1 F ceramic
Rev 1.0, Dec. 01, 2006
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W40S11-02
Ordering Information
Ordering Code W40S11 Freq. Mask Code -02 Package Name H X Package Type 28-pin SSOP (209-mil) 28-pin TSSOP (173-mil)
Package Diagrams
28-Lead Thin Shrunk Small Outline Package (4.40-mm Body)
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.16 gms
4.30[0.169] 4.50[0.177]
6.25[0.246] 6.50[0.256]
PART # Z28.173 STANDARD PKG. ZZ28.173 LEAD FREE PKG.
28
0.65[0.025] BSC. 0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
9.60[0.378] 9.80[0.386]
Ordering Information
Ordering Code W40S11 Freq. Mask Code -02 Package Name H X Package Type 28-pin SSOP (209-mil) 28-pin TSSOP (173-mil)
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, Dec. 01, 2006
Page 9 of 9

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